1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to an efficient method for measuring current consumption time rate of change to prevent voltage droop.
2. Description of the Relevant Art
Both power consumption and voltage droop of modern integrated circuits (IC's) has become an increasing design issue with each generation of semiconductor chips. IC power dissipation and voltage droop constraints are not only an issue for portable computers and mobile communication devices, but also for high-performance superscalar microprocessors, which may include multiple processor cores, or cores, and multiple pipelines within a core. The geometric dimensions of devices and metal routes on each generation of cores are decreasing. Superscalar designs increase the density of integrated circuits on a die with multiple pipelines, larger caches, and more complex logic. Therefore, the number of nodes and buses that may switch per clock cycle significantly increases.
Cross-capacitance effects grow with decreasing geometric dimensions. Cross-capacitance increases the power consumption and noise effects on the chip. Also as IC's have achieved greater operational frequencies, these circuits again increase power consumption and have become more sensitive to parasitic inductance effects that also result from decreasing geometric dimensions. Some origins of parasitic inductance include bond wires, IC package leads, external supply lines, and wide buses.
Parasitic inductance increase transmission line effects on a chip such as ringing and reduced propagation delays. Also, a simultaneous switching of a wide bus may cause a significant voltage drop if a supply pin served all of the line buffers on the bus. This voltage droop, ΔV, is proportional to the expression L di/dt, wherein L is the parasitic inductance and di/dt is the time rate of change of the current consumption. If a large number of nodes in addition to buses switched simultaneously, a significant voltage drop may occur. Now a node that holds a logic high value may experience a voltage droop that reduces its voltage value below a minimum threshold. For memories and latches without recovery circuitry, stored values may be lost.
One manner to reduce voltage droop is to reduce the operational frequency of the IC. Although, this method may reduce the overall current consumption, a simultaneous switching of numerous nodes and signal lines still may reduce a node's voltage value to below a minimum threshold. Therefore, this reduction in performance still does not protect against voltage droop. The node capacitance switching may decrease for certain blocks and/or units in the chip by disabling the clock to these areas with qualified enable signals during periods of non-use. However, during use of these units, again, simultaneous switching of numerous nodes and signal lines may occur and the voltage droop problem still exists.
Another method for reducing voltage droop, ΔV, is reducing parasitic inductance, L, such as placing an external capacitor between the supply leads. This external capacitance creates a passive bypass that reduces the supply line oscillation due to external inductances. However, it does not significantly reduce the oscillation caused by internal inductances. Another manner to reduce inductance effects includes placing an on-chip capacitor between the internal supply leads. The capacitor acts as a bypass in the same manner as an external capacitor. However, in order to be effective, the internal capacitor must be very large, which requires a significant portion of the chip area. This manner is undesirable when minimization of the die area is needed.
Other methods to reduce parasitic inductance effects include separating power pins for input/output (I/O) pads and for the core, placing multiple supply and ground reference pins over the die, and distribute gate oxide capacitors across the die, especially under data buses. Again, these methods may not be desirable when die minimization is required.
The above methods are passive. Active compensation approaches can also be used, and are broken down into proactive and reactive. Reactive methods detect and reduce the time rate of change of current consumption, di/dt. In order to be beneficial and to prevent a voltage droop from lowering a node voltage below a minimum threshold, these reactive methods must detect and initiate a current reduction within a predetermined time window. There are reactive methods that use analog detection and a subsequent frequency reduction in order to decrease parasitic inductance effects. However, frequency reduction does not remove the electrical problems as described above for operational frequency reduction. Also, design complexity and on-chip area increase with a dynamic frequency control system and associated chip level interface issues.
Further, a di/dt detector and subsequent response mechanism are most beneficial in a computer system when they are deterministic. In other words, the detector and mechanism should provide the same results, or frequency changes, from part-to-part, system-to-system, and run-to-run. The reason for this requirement is Original Equipment Manufacturers (OEMs) using the processor in one of their systems need to provide performance guarantees to customers. Customers and OEMs need to replicate the benchmarks and performance measures at different times and in different locations. If this replication cannot be done within a tight tolerance (i.e. +/−1.5%), then the detector and response mechanism need to be turned off. Now the detector and mechanism take up area on the die without performing useful work to improve performance and voltage droop reduction.
Analog sensors, such as temperature sensors and/or an ammeter, are able to provide accurate power estimations, and thus, current consumption, but all of them are environment dependent. Variations in fabrication processes, ambient temperature, power supplies, and the quality of the heat removal solution alter the measurements of analog sensors.
In view of the above, efficient methods and mechanisms for providing a proactive, digital real-time voltage droop detection and subsequent voltage droop reduction are desired.